100 MHz HCSL MEMS oscillator — active, industrial-rated
HCSL (High-Speed Current Steering Logic) is the typical reference clock format for PCIe, SATA, and Ethernet PHYs — the 100 MHz frequency aligns directly with PCIe Gen 1/2/3 reference clock requirements. Supply voltage spans 2.25 V to 3.6 V, which covers the common 2.5 V and 3.3 V rails used in networking and computing platforms. The wide range also allows the oscillator to share a rail with a 1.8 V core logic supply if the regulator output is set within the window. The 6-VDFN package measures 2.50 mm × 2.00 mm, a compact footprint that fits tight channel spacing on a line card.
This is useful for battery-backed or duty-cycled systems where the reference clock can be gated off between active periods without a separate load switch. When enabled, the maximum supply current is 42 mA at 100 MHz HCSL output. The HCSL swing is typically 700-800 mV peak-to-peak into a 50-Ω termination to ground, which sets the AC coupling capacitor selection for the downstream receiver.