156.25 MHz HCSL clock source for SerDes and PCIe reference
The DSC1104DI1-156.2500 is a MEMS-based XO (Standard) delivering a 156.25 MHz HCSL output — the exact frequency and logic family used as the reference clock for 10GbE SerDes, PCIe Gen 3/4, and many FPGA transceiver banks. HCSL (High-Speed Current Steering Logic) swings 700-900 mV peak-to-peak into a 50-Ω terminated differential pair; the 156.25 MHz edge rate is fast enough that the PCB trace length mismatch between the P and N legs should stay under 5 mils to keep the crossing point centered.
Supply range spans 2.25V to 3.6V — it runs from a 2.5V or 3.3V rail directly, no extra LDO needed; the 42 mA max draw at 3.3V (139 mW) is manageable in the 2.5 mm × 2.0 mm 6-SMD package as long as the board has a copper pour under the part.