100 MHz HCSL clock source for PCIe reference
The DSC1104DI1-100.0000T is a 100 MHz MEMS-based oscillator with HCSL output — the differential current-mode logic that PCIe Gen1 through Gen5 reference clocks expect. No external termination resistors to ground are needed; the HCSL swing is defined by the current delivered into a 50-Ohm load to ground. For a 10 Gb/s serial link, that stability margin keeps the bit-error rate within the PHY's CDR capture range.
Supply flexibility and standby power budget
The 2.25V to 3.6V supply range spans 2.5V and 3.3V rails — no extra LDO is required when the board has both. At 42 mA max active current, the oscillator's draw is small compared to the FPGA core, but the 95 µA standby current (disable state) matters for a line card that must retain clock reference while the main rail is gated. The standby (power-down) function on pin 1 shuts the output to high-Z and drops current to 95 µA max. That is low enough to keep the oscillator powered from a small supervisory rail without draining the hold-up capacitor.
Microchip lists the DSC1104DI1-100.0000T as Active.