100 MHz MEMS XO with HCSL output
Frequency stability is rated at ±20 ppm, which keeps the 100 MHz carrier within tight timing margins for SerDes, FPGA transceivers, and network synchronisation.
Housed in a 6-VDFN package measuring 3.20 mm × 2.50 mm with a seated height of 0.90 mm — a standard small-outline clock footprint that shares land pattern with many 6-pin oscillators. Surface-mount reflow profile per JEDEC MSL level applies.
