HCSL is the typical reference clock for PCIe, SATA, and other high-speed serial interfaces — the ±20 ppm holdover meets the ±300 ppm total budget most PCIe Gen1/2/3 controllers require, with margin for the rest of the clock tree.
Power draw and standby behavior
That 95 µA is low enough to leave the oscillator powered from a battery-backed rail during system sleep — no need for a load switch or a separate always-on regulator just for the clock.
