125 MHz HCSL reference for PCIe and SerDes clock trees
HCSL (High-Speed Current Steering Logic) provides a differential swing that drives 50-Ω terminated lines directly, eliminating the external termination resistor network required by LVPECL. The ±10 ppm frequency stability holds the reference within the PCIe Gen 3 / Gen 4 spread-spectrum tracking budget without external trim capacitors or a VCXO. For a 125 MHz clock, ±10 ppm equals ±1250 Hz of absolute error — well within the 300 ppm capture range of a typical SerDes CDR.
Wide supply and standby power-down
The 42 mA max supply current at 125 MHz HCSL is typical for this output family — the differential output stage draws the majority of the current.
Industrial temperature and MEMS reliability
The 3.20 mm × 2.50 mm 6-SMD no-lead package (0.90 mm seated height) fits the same footprint as standard quartz oscillators. No via-in-pad or thermal relief required — the no-lead pads are soldered directly to the PCB land pattern.