200 MHz HCSL clock source for high-speed serial links
The 200 MHz frequency directly serves the 100 MHz base-rate multiplied by PLLs, or drives a SerDes reference at the line rate. Operating from 2.25V to 3.6V, it spans 2.5V and 3.3V supply rails without a separate regulator. The ±25 ppm frequency stability holds the reference tight enough for 1 GbE and PCIe Gen 1/2/3 without external trimming.
Industrial temperature grade and MEMS ruggedness
The 6-VDFN package (3.20mm x 2.50mm, 0.90mm seated height) is a low-profile, leadless land-grid array.
Standby power-down for system-level gating
This is useful for battery-powered or duty-cycled designs where the oscillator is the last block to shut down before sleep. At full operation, the core draws 42 mA max at 200 MHz — a known budget for the 3.3V rail.
No pin-compatible second source is registered, but the DSC1104 series shares the same footprint across frequency variants.