200 MHz HCSL clock source for SerDes and FPGA reference
The DSC1104CI2-200.0000 delivers a 200 MHz HCSL output from a MEMS resonator — a clean differential clock for PCIe Gen1/2/3 reference, 10GbE SerDes, or FPGA GTY transceivers. The HCSL swing and common-mode levels are specified for direct AC-coupling to the receiver without external level translation.
Industrial temperature and supply tolerance
Supply voltage spans 2.25 V to 3.6 V, so a single BOM line serves 2.5 V and 3.3 V rails without a separate regulator or level shifter.
Standby power-down and package footprint
The 6-VDFN package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm, fitting under low-profile heatsinks or in tight card-edge zones.