100 MHz HCSL clock from a MEMS resonator
The HCSL output is the differential signalling standard used for PCIe reference clocks and Ethernet PHY reference inputs; it swings 700–900 mV peak-to-peak into a 50-Ω terminated pair, which means it drives a differential line directly without an external level translator. Supply voltage spans 2.25V to 3.6V, so the same BOM line works on a 2.5V or 3.3V rail — no extra regulator needed. The ±25 ppm frequency stability covers temperature, supply, and ageing combined, which is tight enough for most 1000BASE-T Ethernet and PCIe Gen 1/2/3 reference clock jitter budgets without stepping up to a TCXO.
Standby power-down for intermittent duty
The 42 mA max active draw is typical for a 100 MHz HCSL oscillator; the differential output stage accounts for most of it, so the current is fairly independent of the load capacitance.