HCSL output for PCIe and high-speed serial clocks
HCSL (High-Speed Current Steering Logic) delivers a 0.7 Vpp swing into a 50-Ω terminated line, which means this oscillator mates directly with PCIe, SATA, or Ethernet PHY reference inputs without an external level translator.
Frequency stability is ±25 ppm across the full temperature and voltage range — tight enough for 1000BASE-T Ethernet and PCIe Gen 1/2/3 reference clock jitter budgets. For applications requiring ±20 ppm or better, a different stability grade in the DSC1104 family would be needed.
Standby power-down and package footprint
The 6-SMD no-lead package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm, fitting tight board stacks in handheld or embedded designs.