100 MHz HCSL clock source with MEMS reliability
The HCSL output is the common clock format for PCIe reference clocks and high-speed serial interfaces, making this a direct fit for server, networking, and FPGA-based designs that require a clean 100 MHz differential clock.
Standby mode and supply flexibility
This allows the system to shut down the clock tree when the associated logic is idle, saving power in battery-powered or thermally constrained designs. The supply voltage range of 2.25V to 3.6V covers common 2.5V and 3.3V rails without an external regulator. The 6-SMD, no-lead package (3.20mm x 2.50mm) is a standard MEMS oscillator footprint, compatible with many existing XO layouts.
