125 MHz LVDS clock source with ±10 ppm stability
The DSC1103DL5-125.0000: The LVDS output pairs well with high-speed serial links — the differential swing keeps jitter low and common-mode noise rejection high, which matters for 125 MHz clocking into an FPGA or SerDes reference.
Check the MSL before the bake cycle — MEMS oscillators typically ship at MSL 1 or 2, but the reel label confirms the floor life. If it is MSL 2, a 1-hour bake at 125°C before reflow avoids popcorning in the no-lead package.