125 MHz LVDS clock source with ±10 ppm stability
The DSC1103DI5-125.0000: The LVDS signalling pair keeps edge rates clean over short PCB traces to FPGAs, SerDes, or Ethernet PHYs without an external terminator — the receiver's 100 Ω differential termination is sufficient.
That disable current is low enough to leave the oscillator powered from a battery-backed rail during sleep — no external load switch needed. The 32 mA max active current is typical for a 125 MHz LVDS driver; the MEMS resonator itself draws negligible current compared to the output buffer.
