400 MHz LVDS clock source for high-speed timing
The DSC1103DI2-400.0000T is a 400 MHz XO (Standard) with LVDS output, built on a MEMS resonator — no quartz crystal inside. The LVDS signalling keeps jitter low and common-mode noise rejection high over twisted-pair or differential PCB traces, which is why this part lands in SERDES reference clocks, FPGA transceiver banks, and 10G Ethernet PHY timing.
Supply range and standby for system power budgeting
The supply voltage spans 2.25V to 3.63V, covering common 2.5V and 3.3V rails without an external LDO.
