200 MHz LVDS reference clock with MEMS reliability
Output is LVDS, so the differential pair keeps jitter low over trace lengths up to a few inches — a natural fit for clocking an FPGA gigabit transceiver or a high-speed ADC/DAC without an external fanout buffer.
Wide supply range and low disable current
Supply voltage spans 2.25 V to 3.63 V — covers both 2.5 V and 3.3 V rails without needing a separate voltage variant in the BOM; just one line item for both power domains.
The 6-SMD no-lead package (2.50 mm x 2.00 mm footprint, 0.90 mm seated height) is a standard MEMS oscillator land pattern shared across the DSC1103 family — swapping to a different frequency in the series keeps the same PCB footprint.