LVDS output at 148.5 MHz – signal-integrity fit for video clocks
The DSC1103DE1-148.5000T delivers a 148.5 MHz LVDS output from a MEMS-based XO — the differential signalling keeps the edge rate clean across a few inches of 100-Ω terminated trace, which is the typical run from the oscillator to the FPGA or serializer in a broadcast-video timing tree.
Standby function and 95 µA disable current
Active-high standby pin; the output goes high-impedance when disabled, so the downstream receiver sees a tri-state line rather than a stuck level.
Active production – design-in ready
Availability confirmed at RFQ.