106.25 MHz LVDS clock for industrial serial links
The DSC1103CL5-106.2500 is a MEMS-based XO (Standard) delivering a 106.25 MHz LVDS output — a common reference frequency for 10GbE, Fibre Channel, and PCIe Gen 1/2 clocking. The LVDS differential pair keeps jitter low over board traces longer than a few inches, which matters when the oscillator sits on a different board edge from the SerDes. The ±10 ppm frequency stability holds the link timing across that full temperature sweep without a separate TCXO.
The 2.25V to 3.63V supply range covers 2.5V and 3.3V rails without an external regulator — useful when the same BOM runs on both voltages across product variants.
6-SMD footprint and board fit
Housed in a 3.20 mm x 2.50 mm 6-SMD no-lead package, 0.90 mm seated height. The small footprint leaves room for passives on dense SerDes layouts. Surface-mount reflow follows standard JEDEC profiles for MEMS oscillators — no special bake-out required above MSL 1, but confirm the reel date code if the part has been in storage beyond the floor-life label.