337.6 MHz LVDS clock for SERDES and FPGA reference
The DSC1103CI5-337.6000 is a MEMS-based XO (Standard) oscillator delivering a 337.6 MHz LVDS output — a frequency commonly used as a reference clock for high-speed SERDES transceivers, FPGA gigabit transceivers, and Ethernet PHYs that require a clean differential clock above 300 MHz.
Supply range and standby power-down
MEMS reliability and package footprint
Housed in a 6-VDFN package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm, the footprint is compatible with standard 6-pin oscillator land patterns; the 0.50 mm pad pitch requires careful fan-out on two-layer boards.
Active production — no end-of-life watch
No NRND or EOL notice has been issued for this order code.