233.3333 MHz LVDS clock with ±10 ppm hold
The DSC1103CI5-233.3333: A MEMS-based XO (Standard) delivering 233.3333 MHz on an LVDS output — the ±10 ppm frequency stability means the clock edge jitter stays within the timing budget for a 10 GbE SERDES reference or a high-speed ADC sample clock without an external PLL cleanup.
Standby power-down drops to 95 µA
Industrial temp grade and 6-SMD footprint
Housed in a 3.20 mm x 2.50 mm 6-SMD no-lead package (0.90 mm seated height) — the small footprint and low profile suit dense PCB layouts, but the no-lead land pattern requires a solder-paste stencil aperture matched to the pad geometry for reliable fillet formation.
