140 MHz LVDS clock source with MEMS reliability
Supply voltage spans 2.25V to 3.63V, so the same part works on 2.5V or 3.3V rails without a separate LDO.
When enabled, the oscillator draws 32 mA max at 140 MHz, which is typical for an LVDS output at this frequency and well within the budget of a medium-density FPGA or SoC reference clock.
Housed in a 6-SMD, no-lead package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm—a compact footprint that fits tight channel spacing on a multi-lane SerDes or Ethernet PHY layout. The no-lead package requires a solder-paste stencil with aperture matching the pad geometry; standard reflow profiles for lead-free assembly apply.