100 MHz LVDS MEMS oscillator — ±10 ppm stability
LVDS signalling keeps the edge rates clean for 100 MHz clock distribution to FPGAs, SerDes, or high-speed ADCs — the differential pair rejects common-mode noise on the board.
Supply range and standby power-down
Supply voltage spans 2.25 V to 3.63 V, covering 2.5 V and 3.3 V logic rails without an external regulator — one BOM line serves both rail voltages. Active current draw is 32 mA max at 100 MHz — the LVDS output stage is the dominant consumer, not the MEMS core.
Package and board layout — 6-SMD, 3.2×2.5 mm
6-SMD, No Lead package measuring 3.20 mm × 2.50 mm with a seated height of 0.90 mm — the compact footprint fits dense PCB layouts where a larger can oscillator would crowd adjacent components. Surface-mount on standard FR-4 with no special pad geometry — the six pads include two for the differential output, two for supply and ground, and two for the standby control and no-connect.