156.25 MHz LVDS reference for SerDes and FPGA clock trees
The DSC1103CI2-156.2500 is a MEMS-based XO delivering a 156.25 MHz LVDS output — a common reference frequency for 10 Gigabit Ethernet SerDes, PCIe Gen 3, and FPGA transceiver blocks. The LVDS differential pair provides the low-jitter edge rates these interfaces require, with a typical phase jitter that keeps the bit-error rate within the link budget. It operates from a 2.25V to 3.63V supply, covering both 2.5V and 3.3V rails without a separate LDO. The wide range also absorbs rail droop during load transients, which matters when the oscillator shares a supply with a switching regulator.
The 6-SMD no-lead package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a compact footprint that fits dense timing arrays on multi-layer boards. The no-lead construction reduces parasitic inductance on the output path compared to a gull-wing package, which helps preserve the LVDS signal integrity at 156.25 MHz.