106.25 MHz LVDS clock with MEMS resonator
For a 106.25 MHz reference clock feeding an FPGA or a SerDes transceiver, that stability keeps the bit-error rate within the link budget without external temperature compensation.
Supply range and standby power-down
Supply voltage spans 2.25V to 3.63V, covering common 2.5V and 3.3V rails without an additional regulator. The wide tolerance also absorbs rail droop during load transients — useful when the oscillator shares a supply with switching converters.
6-SMD no-lead package
Housed in a 6-SMD, no-lead package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm.