The LVDS output delivers a differential signal with 350 mV typical swing into a 100-Ω termination — this is the signalling standard for 122.88 MHz reference clocks feeding a SerDes or FPGA PLL, where single-ended CMOS would suffer common-mode noise coupling across the board.
Supply range and power-down current
The supply voltage spans 2.25 V to 3.63 V, covering the common 2.5 V and 3.3 V digital rails without an external regulator.
Package footprint and board layout
The 6-SMD no-lead package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a compact footprint that fits the same land pattern as many 3.2 x 2.5 mm quartz oscillators, so a board originally laid out for a quartz XO can often accept this MEMS part without a layout change.