100 MHz LVDS clock for industrial timing
The LVDS output delivers a differential signal with low jitter, suitable for clocking high-speed ADCs, FPGAs, or SERDES interfaces that need a clean 100 MHz reference.
Supply range and standby power-down
Supply voltage spans 2.25V to 3.63V, covering both 2.5V and 3.3V rails without an extra regulator — one BOM line serves either power domain. Active current is 32 mA max at 100 MHz, typical for an LVDS MEMS oscillator at this frequency.
Housed in a 6-SMD, no-lead package measuring 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a standard 3.2 x 2.5 mm oscillator footprint that fits most high-density designs.