MEMS resonator vs quartz — what the 156.25 MHz LVDS output buys the design
This means no crystal aging drift over the first year, no startup reliability concerns from mechanical shock, and a typical lead time that avoids the 8–16 week backlog common on quartz at 156.25 MHz. The LVDS output at 156.25 MHz is the reference clock for 10G Ethernet PHYs, FPGAs with gigabit transceivers, and SERDES framers. LVDS gives a 350 mV swing into a 100-Ω differential termination — low enough to keep radiated emissions under control without external filtering, and fast enough edge rate to drive a point-to-point trace up to about 12 inches on standard FR-4.
The supply range is 2.25V to 3.63V — it runs directly off a 3.3V or 2.5V rail without an intermediate LDO. The 32 mA max supply current at 156.25 MHz is typical for an LVDS oscillator at this frequency; the 95 µA disable current (Standby function) lets a power-management controller shut the clock off during system sleep and keep the battery drain negligible.
Package and temperature — board-fit checklist
6-SMD no-lead package, 3.20 mm x 2.50 mm, 0.90 mm seated height. The land pattern is the same as a standard 6-pin quartz oscillator footprint — drop-in compatible with existing board layouts that expect a 3.2 x 2.5 mm XO.