74.25 MHz LVDS clock source — MEMS, not quartz
The output is LVDS, a differential pair that keeps noise off the clock line over short PCB traces. At 74.25 MHz, this frequency is a standard video pixel clock for 1080p and 4K formats — it also shows up in serial data links and FPGA reference clocks. The ±25 ppm frequency stability means the clock edge jitter stays tight enough for most serial transceivers without a separate PLL cleanup.
Supply range and standby power-down
The 6-SMD no-lead package measures 3.20 mm x 2.50 mm, seated height 0.90 mm — a compact footprint that fits tight board layouts.