74.25 MHz LVDS clock for video timing
The DSC1103CE2-074.2500 is a MEMS-based XO delivering a 74.25 MHz LVDS output — the exact pixel clock for 720p video standards and common in broadcast and display interface timing chains.
The supply voltage range of 2.25V to 3.63V covers 2.5V and 3.3V rails commonly found in FPGA and SoC clock trees, simplifying rail selection.
Availability confirmed at RFQ.
