MEMS oscillator with LVDS output for industrial clock trees
LVDS signalling provides low-jitter, differential clock distribution for high-speed interfaces — the 100 MHz output is a common reference for Ethernet PHYs, FPGAs, and SoC clock inputs.
Standby function and supply voltage flexibility
The supply voltage range of 2.25V to 3.63V covers common 2.5V and 3.3V rails without an external regulator.
Active lifecycle — production status confirmed
6-VDFN package and board integration
Housed in a 6-VDFN package measuring 5.00mm x 3.20mm with a seated height of 0.90mm. The 0.90mm height suits tight card-edge or mezzanine spacing.