The LVDS signal pair drives differential clock inputs on FPGAs, SERDES transceivers, or high-speed ADCs directly, with the 32 mA max supply current covering the full 120 MHz output swing. Supply voltage spans 2.25V to 3.63V, so the same oscillator can run from a 2.5V or 3.3V rail without a separate LDO.
Industrial temperature grade and board-level fit
This makes the part suitable for outdoor telecom base stations, factory-floor PLCs, and engine-bay control modules where the ambient temperature cycles daily. The 6-SMD, no-lead package measures 5.00 mm x 3.20 mm with a seated height of 0.90 mm — a compact footprint that fits tight PCB layouts alongside the processor or FPGA it clocks.