100 MHz LVDS MEMS oscillator – active production
The LVDS output pairs with high-speed digital loads — FPGA reference clocks, SERDES, or Ethernet PHY — where the differential swing rejects common-mode noise on the clock trace. Supply voltage spans 2.25V to 3.63V, so a single BOM line covers 2.5V and 3.3V clock domains without a separate regulator. The 6-SMD no-lead package measures 5.0 mm × 3.2 mm with a seated height of 0.9 mm max — standard footprint that places without tombstoning risk on a typical reflow profile. Check the MSL before you place it; MEMS oscillators generally ship MSL 1, but the reel label is the final word.
