25 MHz LVDS clock source — active and available
The DSC1103AI5-025.0000T: The LVDS output pairs directly with high-speed SERDES, Ethernet PHY reference clocks, and FPGA clock inputs that expect a differential 100-ohm terminated signal — no external level translation needed.
Supply range and standby power-down
Operates from a 2.25 V to 3.63 V supply, covering common 2.5 V and 3.3 V rails without an extra regulator.
Availability confirmed at RFQ.
