LVDS clock at 25 MHz with MEMS reliability
The DSC1103AI5-025.0000 is a 25 MHz MEMS-based XO with LVDS output, ±10 ppm frequency stability, and a 2.25 V to 3.63 V supply range — the LVDS pair delivers a low-jitter differential clock that rejects common-mode noise on long PCB traces or cables.
Standby mode and supply flexibility
The 2.25 V to 3.63 V supply range covers 2.5 V and 3.3 V rails common in FPGA and SoC clock trees, so no extra level translator is needed between the oscillator and the LVDS receiver.
