MEMS timing at 112 MHz with LVDS output
The LVDS output pair requires a 100-Ohm termination resistor across the differential traces at the receiver — without it the signal amplitude collapses and the receiver misses edges. Supply range spans 2.25 V to 3.63 V, so the same oscillator serves both a 2.5 V FPGA bank and a 3.3 V PHY without a dedicated LDO. The 32 mA max supply current is typical for an LVDS output at this frequency; budget it into the rail's total current draw.
Industrial temperature grade and standby power-down
For a battery-backed real-time clock or a sensor node that sleeps between bursts, this keeps the oscillator's idle draw below the self-discharge rate of a coin cell.