LVPECL output at 125 MHz — MEMS-based timing
The DSC1102NE1-125.0000 is a MEMS-based XO (Standard) delivering a 125 MHz LVPECL clock from a 2.25V to 3.6V supply rail. The LVPECL output provides the differential swing needed for low-jitter clock distribution to FPGAs, SERDES, or Ethernet PHYs at 125 MHz — a common reference for Gigabit Ethernet and 10GBase-R.
The 6-SMD, No Lead package (7.00mm x 5.00mm, 0.90mm seated height) is a standard oscillator footprint that reflows with a typical lead-free profile.
The active max supply current is 58 mA, typical for a 125 MHz LVPECL oscillator driving a 50-ohm terminated line.