125 MHz LVPECL clock source for high-speed interfaces
The DSC1102DI1-125.0000T delivers a 125 MHz LVPECL output from a MEMS resonator, making it a direct-fit timing reference for 10GbE, Fibre Channel, and FPGA transceiver banks that require a low-jitter differential clock. The LVPECL swing provides the edge rate needed to drive 50-ohm terminated lines without additional buffering. Supply voltage spans 2.25V to 3.6V, so the same BOM line works on a 2.5V or 3.3V rail — no external regulator needed for voltage translation.
Industrial temperature grade and standby power
The DSC1102 series is the base product number; the full order code DSC1102DI1-125.0000T is the specific frequency and stability variant. No known counterfeit risk at this lifecycle stage, but date-code traceability is standard on all lots we supply.
Package and board-mounting note
Housed in a 6-SMD no-lead package measuring 2.50 mm × 2.00 mm with a seated height of 0.90 mm.