MEMS clock source for 200 MHz LVPECL timing
LVPECL output at 200 MHz provides the low-jitter, differential signalling needed for high-speed SERDES, FPGA reference clocks, and 10G Ethernet PHY reference inputs — the 58 mA max supply current reflects the output driver bias, not the MEMS resonator core.
Supply range and standby power-down
Supply voltage spans 2.25V to 3.6V, covering common 2.5V and 3.3V rails without an external LDO — the wide range simplifies rail assignment on multi-voltage boards.
Housed in a 6-SMD, No Lead package measuring 3.20mm x 2.50mm with a seated height of 0.90mm — the compact footprint suits tight channel spacing on line cards and mezzanine boards. Surface-mount assembly with no through-hole leads; the 0.90mm height keeps the oscillator below the keep-out zone of adjacent BGA components on the same side of the board.