MEMS XO with LVPECL output – fit for high-speed clock trees
LVPECL is a differential output standard — it drives 50-ohm terminated lines directly, making this part a natural fit for Gigabit Ethernet PHY reference clocks, FPGA/ASIC high-speed inputs, and SerDes where single-ended CMOS edges would introduce jitter. Supply voltage range is 2.25V to 3.6V — the oscillator runs off a 2.5V or 3.3V rail without an intermediate regulator, but the LVPECL output swing scales with Vdd, so the receiver's common-mode range must accommodate the rail choice. That stability band covers the full temperature range and aging — a fixed 10 ppm window is tighter than many quartz oscillators in the same price tier, which often spec ±25 ppm or ±50 ppm over temperature alone.
For a line card that sleeps between packet bursts, this saves the 58 mA operating current without a separate load switch.
Package and layout – 6-SMD no-lead
Housed in a 3.20 mm x 2.50 mm 6-SMD no-lead package (0.90 mm seated height). The compact footprint suits dense PCB layouts where a standard 7x5 mm oscillator would crowd routing channels.