MEMS-based XO with LVPECL output at 100 MHz
LVPECL is a differential logic family that requires a DC-biased termination (typically 50 Ω to VCC – 2 V) — the 100 MHz frequency means the oscillator's phase jitter directly impacts the bit-error rate of the downstream serializer or FPGA transceiver.
Supply voltage and power-down current
Operates from a single 2.25V to 3.6V supply, covering both 2.5V and 3.3V logic rails without a separate regulator. The max supply current is 58 mA — the LVPECL output stage draws a constant bias current regardless of frequency, so this figure sets the regulator's load budget.
Industrial temperature range and frequency stability
Housed in a 6-SMD, No Lead package measuring 5.00 mm × 3.20 mm with a seated height of 0.90 mm. The footprint is standard for 6-pin oscillators — the no-lead construction reduces parasitic inductance compared to a gull-wing lead, which matters for the LVPECL edge rates at 100 MHz.
No direct pin-compatible replacement is listed; the DSC1102 series shares the same footprint and pinout across frequency variants, so a different frequency in the same series would fit the same PCB layout.