412.5 MHz LVPECL clock from a MEMS resonator
The DSC1102AE5-412.5000T is a MEMS-based XO (Standard) that delivers a 412.5 MHz LVPECL output — a clean reference for high-speed FPGA transceivers, SerDes PLLs, or 10G Ethernet MAC/PHY clock trees where the differential signal keeps common-mode noise out of the timing path.
Supply flexibility and power-down control
At 58 mA max supply current, the power draw is modest for a 412.5 MHz LVPECL source. The output goes high-Z in standby, so the downstream receiver sees a quiet line.
Housed in a 6-SMD, No Lead Exposed Pad package measuring 7.00 mm × 5.00 mm with a seated height of 0.90 mm — a standard footprint that matches many 7×5 mm oscillators.
No direct pin-compatible replacement or second-source is recorded, but the DSC1102 family shares the same footprint and supply range — confirm the output type and frequency before substituting.