MEMS clock source for tight timing budgets
Supply voltage spans 2.25 to 3.6 V, covering 2.5 V and 3.3 V logic rails with margin. The 95 µA max supply current at 100 MHz makes it a fit for power-sensitive interfaces like Ethernet PHY reference clocks or FPGA configuration oscillators where every milliwatt counts.
Standby function and power-down control
This allows the system to gate the clock without an external load switch — useful for power-gated domains in battery-operated designs.
Package profile and board layout
The 3.20 x 2.50 mm 6-SMD no-lead package (0.90 mm seated height) fits tight layout zones. No external capacitors or termination resistors are needed — the CMOS output drives a standard 15 pF load directly.