84.672 MHz MEMS oscillator – what it buys the clock tree
That frequency sits in the sweet spot for 100BASE-T Ethernet MAC/PHY reference clocks and USB 2.0 high-speed crystal-less controllers – the ±20 ppm absolute pull range (APR) keeps the link timing within the ±100 ppm window those interfaces require. The CMOS output swings rail-to-rail, which mates directly with the clock input of most MCUs, FPGAs, and PHYs.
Package and reflow – 6-VDFN exposed pad
Housed in a 6-VDFN exposed pad package measuring 7.00 mm x 5.00 mm with a seated height of 0.90 mm. Standard FR-4 with a 4-layer stack handles the footprint cleanly. The output goes high-impedance in standby, so the downstream clock input should have a pull-down or be tri-stated to avoid floating gates.