The 133 MHz output is a common reference for Gigabit Ethernet PHYs, high-speed serial transceivers, and FPGA clock inputs that need a clean 133 MHz source without a PLL multiplication. The ±25 ppm stability over -40°C to +85°C means the oscillator holds its frequency within 0.0025% across the full industrial temperature range. For a 133 MHz clock, that is a maximum drift of about 3.3 kHz – well within the capture range of a typical Ethernet PHY or FPGA MMCM.
Microchip lists the DSC1025BI2-133.0000T as Obsolete. For a BOM line that must stay active, a pin-compatible MEMS oscillator from the same package family (5.0 mm × 3.2 mm, 4-SMD) with the same 2.5V supply and CMOS output is the practical migration path. Confirm the replacement's frequency stability and standby logic polarity before respinning the board.
Standby function and supply current – power budget fit
The oscillator draws 10 mA max when enabled and 1 µA max in standby (disable) mode. The standby pin lets a battery-powered system cut the oscillator's draw to near-zero during sleep, preserving the battery for the active duty cycle. The 2.5V supply rail is common in low-power FPGA and MCU designs. If your board only has a 3.3V rail, the DSC1025BI2 cannot be used directly – it requires a 2.5V supply or an LDO to drop from 3.3V.