MEMS resonator with AEC-Q100 grade
1.485 MHz fixed frequency — video sync reference
The 1.485 MHz output is the standard pixel clock for 1080i/720p HD-SDI video and a common audio master clock. At ±25 ppm frequency stability, the jitter contribution stays low enough for the serialiser to meet SMPTE 424M timing margins without an external VCXO.
Wide supply and standby power-down
Supply voltage spans 1.8 V to 3.3 V, so the same oscillator works across a 1.8 V FPGA bank and a 3.3 V ASIC without a level translator.
Industrial temp range and small footprint
The 2.50 mm x 2.00 mm 4-SMD no-lead package takes up less board area than a typical 3.2 mm x 2.5 mm quartz can — useful when the layout is tight around the processor.