The DSC1001DI5-047.3885: This is a MEMS-based XO (Standard) producing a 47.3885 MHz CMOS output clock from a 1.8V to 3.3V supply rail, with an Enable/Disable function on the output. The ±10 ppm frequency stability holds the timing budget tight enough for most CAN, LIN, and Ethernet physical-layer reference clocks.
Wide supply range and low power draw
The 1.8V–3.3V supply range lets a single oscillator serve a multi-voltage design — the same BOM line works on a 1.8V FPGA bank and a 3.3V PHY.
Package and board-mounting note
The 4-SMD, No Lead package measures 2.50 mm x 2.00 mm with a seated height of 0.90 mm. The small footprint means the decoupling cap sits right next to the VDD pin — a 100 nF X7R within 1 mm of the pad keeps the supply clean.