14.7456 MHz and ±10 ppm — the clock-tree fit
14.7456 MHz is a standard multiple for CAN bus controllers and Ethernet PHY reference clocks — the frequency divides cleanly to 1.8432 MHz (UART baud-rate base) and 24.576 MHz (audio sample-rate base). The ±10 ppm frequency stability over the full temperature range is tighter than the ±25 ppm or ±50 ppm of commodity quartz oscillators, which matters when the downstream PLL has a narrow pull-in range.
Power-down standby and supply flexibility
The supply voltage spans 1.8V to 3.3V, so the same oscillator works across a 1.8V MCU core rail and a 3.3V peripheral rail without a level translator on the clock line.
The 4-SMD no-lead package measures 2.50 mm × 2.00 mm with a seated height of 0.90 mm — a common footprint shared across the DSC1001 series. The four pads are standard for a MEMS oscillator: power, ground, output, and enable/standby. No external load capacitors are needed; the CMOS output drives directly into the downstream clock input.