66.6666 MHz MEMS clock with ±25 ppm hold
This stability figure covers the combined effects of temperature, supply voltage, and aging, so the clock edge at the receiver stays within a 50 ppm window — tight enough for 100BASE-TX Ethernet and most serial data links without external VCXO tuning. Supply voltage spans 1.8V to 3.3V, letting the same oscillator feed a 1.8V FPGA bank or a 3.3V PHY without a level translator.
AEC-Q100 qualification and package footprint
The 4-SMD no-lead package measures 3.20 mm x 2.50 mm with a seated height of 0.90 mm — a compact footprint that fits tight board stacks in engine control units, ADAS modules, or infotainment head units. For a 66.6666 MHz clock driving a gigabit PHY reference, the MEMS construction holds the ppm budget over the product lifetime without recalibration.
Product status is Active.