For a 133 MHz clock, that translates to a worst-case drift of ±6.65 kHz — adequate for most microcontroller and FPGA reference clocks, but check if your PLL jitter budget allows that much wander.
Supply flexibility and standby control
Supply voltage spans 1.8V to 3.3V — one BOM line covers 1.8V, 2.5V, and 3.3V logic domains without a separate regulator.
