New-production stock is not available from the factory; any supply comes from surplus inventory held by independent distributors.
15 ns propagation delay — what it buys you
The 15 ns pin-to-pin propagation delay (tPD) sets the timing budget for address decoding, state-machine sequencing, or bus-interface glue logic. At 5V supply, this speed grade supports system clocks up to roughly 50-60 MHz in registered mode, assuming the macrocell clock-to-output delay and external routing fit within one cycle. For slower legacy buses (8-16 bit at 10-20 MHz), the 15 ns part provides comfortable margin.
10 macrocells — logic capacity ceiling
Ten macrocells, each configurable as registered or combinatorial output with programmable polarity. This is a 22V10-class device — the '10' in the series name. The 24-pin DIP allocates 10 dedicated I/O pins plus 2 clock/input-only pins. For a design that needs more than 10 registered outputs or more than 12 total inputs, step up to a 22V15 or a CPLD with higher macrocell count.
EE PLD — reprogrammable, no UV eraser needed
The EE (electrically erasable) programmable logic array can be reprogrammed in-circuit or in a programmer socket — no UV window or eraser required. This matters for prototyping and firmware iteration: you can re-program the same device dozens of times. The 'CZ' suffix indicates a 5V-only, 15 ns speed variant in the 22V10 family.
Package and footprint — 24-pin DIP
Through-hole 24-DIP with 0.300-inch (7.62 mm) body width and 0.100-inch pin spacing. The supplier device package is 24-PDIP. This is a legacy footprint — board-level re-spin is required if migrating to a surface-mount alternate such as a PLCC-28 or TQFP-44 package.