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Microchip Technology ATF22V10CQ-15JU — FPGA / CPLD & Programmable Logic

Microchip ATF22V10CQ-15JU EE PLD, 15 ns, 10 Macrocells

MPNATF22V10CQ-15JU
Active

Microchip 22V10 series EE PLD, ATF22V10CQ-15JU, 15 ns speed, 10 macrocells, 5V supply, 28-PLCC (J-Lead) surface-mount package, active lifecycle.

$2.0100Ref. price · indicative, final on quote
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

ATF22V10CQ-15JU specifications
ParameterValue
Series22V10
MountingSurface Mount
Programmable typeEE PLD
Voltage - input5V
Speed15 ns
PackageTube
Case28-LCC (J-Lead)
Number of macrocells10

Product details

15 ns EE PLD — 22V10 architecture in 28-PLCC

The Microchip ATF22V10CQ-15JU is an electrically-erasable programmable logic device (EE PLD) from the industry-standard 22V10 family, offering 10 macrocells with a 15 ns propagation delay. It operates from a single 5V supply and is housed in a 28-lead PLCC with J-leads (11.51x11.51 mm body). This is the part for legacy 5V glue logic, address decoding, bus arbitration, and small state machines where the 22V10 architecture and PLCC footprint are already on the board.

The 15 ns propagation delay (tPD) sets the combinatorial input-to-output path. For a 5V system running a 33 MHz bus (30 ns cycle), this part leaves 15 ns of timing margin after the clock edge for address decode and chip-select generation — enough for a single level of logic without pipeline registers. If your system clock is faster or the decode path has multiple PLD stages, the margin shrinks; verify the worst-case combinatorial path against your setup/hold requirements.

10 macrocells — density for the job

Ten macrocells, each configurable as registered or combinatorial output with programmable polarity. That is the standard 22V10 count — enough for an 8-bit address decoder plus two chip-selects, or a 4-state machine with registered outputs. For designs that outgrow this, the 22V10 family scales to 15 ns in the same PLCC footprint; no board respin needed.

5V supply — legacy rail, no level translation

Single 5V supply. No core/IO split — the entire device runs on the same 5V rail as TTL and HC logic families. In a mixed-voltage board (3.3V MCU, 5V peripheral), the PLD outputs drive 5V logic directly but need level shifters or open-drain buffers to talk to the 3.3V side. The 5V-only supply is a fit signal for existing 5V backplanes and industrial I/O cards.

28-PLCC J-Lead — footprint and rework

The 28-lead PLCC (J-Lead) package measures 11.51x11.51 mm. J-leads allow visual inspection of solder joints and easier hand-rework than QFP or BGA. The footprint is socket-compatible with standard 28-pin PLCC sockets for prototyping or field upgrades. The J-lead form also provides some compliance to board flex — a consideration for high-vibration environments.

For BOM sustainment, this part is available through standard distribution and independent channels; no forced redesign or second-sourcing urgency exists today.

Frequently asked questions

What is the speed of ATF22V10CQ-15JU?

The listed propagation delay (speed) is 15 ns. This is the combinatorial input-to-output timing; for registered operation, the clock-to-output delay and setup time are specified separately in the datasheet.